Integrated circuits have progressed to advanced technologies with smaller feature sizes, such as 32 nm, 28 nm and 20 nm. In these advanced technologies, field-effect transistors (FETs) include three dimensional transistors each having a fin-like FET (FinFET) structure for enhanced device performance. In the FETs, gate stacks include metal for metal electrodes and high-k dielectric material for gate dielectric. However, existing methods and structures have various concerns and disadvantages associated with device performance and reliability. For example, charge scattering is a factor limiting the mobility and scalability of FETs in sub-40 nm technologies associated with metal electrode and high-K gate dielectric. In another example, a three dimensional FinFET structure is complex and expensive in term of cost and performance. Other examples include poor short-channel effect, and mismatch and variability due to dopant fluctuation.
Therefore, there is a need for a structure and method for a FET device to address these concerns for enhanced performance and reduced fabrication cost.